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Monthly Archives: May 2012


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Transistors used for cellular and PCS infrastructure applications are required to amplify signals with a peak-to-average ratio that can exceed 13 dB, resulting in a peak envelope power (PEP) approaching 1 kW. This PEP requirement is a consequence of simultaneous amplification of multiple digitally modulated carriers with a time-varying envelope and requires a load resistance in the neighborhood of 0.3 W. Present load-pull technologies based on mechanical tuners is limited to approximately 1 W at cellular and PCS frequencies, which renders these systems incapable of characterizing transistors under these conditions. Quarter-wave prematching networks have been developed to transform the source- and load-pull domains to lower impedance. A variety of techniques have been used to characterize these quarter-wave networks, including standard vector network analyzer (VNA) error correction. This article presents a further refinement of this characterization technique, which is based on a twotier calibration using 7mm and microstrip thru-reflectline (TRL) calibrations.
RF power amplifiers deployed with first-generation cellular base stations were based on cavity combiners and class C-operated silicon bipolar junction transistors for final-stage devices. Up to 10 independent carriers, each constituting one user typically was combined prior to feeding the antenna. This architecture, coupled with the constant envelope property of FM, virtually eliminated the need for linear transistor operation. However, the linearity requirements placed on transistor performance for second- and third-generation wireless base stations are much more demanding. Wireless service providers require that base stations occupy as little volume as possible and, with the adoption of digital modulation; many carrier signals now have a timevarying envelope. The first requirement implies the elimination of the cavity combiner, thereby requiring simultaneous amplification of several carriers. The second requirement implies that quasilinear class AB amplification be used to maintain the integrity of the modulation envelope.
These changes have drastically changed the way in which high power transistors are characterized. Simultaneous amplification of several carriers, each with a time-varying envelope, results in a peak-toaverage ratio that can exceed 13 dB, leading to a PEP demand approaching 1 kW. At the standard 26 V base station supply voltage, a load resistance in the neighborhood of 0.1 W  is required for generating closed load-pull contours of power, gain, poweradded efficiency and adjacent-channel power rejection.

Present high power load-pull technology is based on either active fundamental re-injection or mechanical tuners1-4. Although in principle an active load-pull system can present an arbitrary load impedance, the architecture of these systems is not amenable to generating the extremely high power necessary to emulate a sub 1 W load at 1 kW PEP. The current state of the art in mechanical tuners is limited in resistance to approximately 1 W, although narrowband systems can go lower5. To overcome the limitation posed by mechanical tuners, many researchers have adopted quarter-wave prematching networks to transform the tuner impedance to lower impedance. With this approach, it is possible to present a sub 1 W resistance necessary for high power transistor characterization.

Traditional Noise Parameter Measurements

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A traditional noise parameter measurement setup, it includes a vector network analyzer (VNA) and a separate noise figure analyzer. For s-parameter measurements, the tuner is set to 50 ohms, and the two RF switches connect the device under test (DUT) to the VNA. For noise measurements, the switches connect the noise source to the DUT input and the noise receiver to the DUT output. An optional load tuner (not shown) is sometimes used when the DUT is highly reflective, to reduce sensitivity to error.

The tuner is pre-characterized at every frequency independently. This means that there is a unique set of tuner positions for each frequency, ensuring a good spread of source impedance points at every frequency. The tuner can be characterized separately, or as part of an in-situ system calibration. The advantage of doing it separately is that the same tuner file can be used for a long time, and then a hybrid in-situ calibration can quickly get the remaining s-parameter blocks.

The in-situ system calibration normally uses two VNA calibrations: a 2-port calibration at the DUT reference planes, and a 1-port s22 calibration at the noise source reference plane. By subtracting error terms, the 2-port x-parameters from the noise source to the DUT can then be determined. If the optional load tuner is used, then a 1-port s11 calibration at the noise receiver reference plane is also used to determine the 2-port s-parameters from the DUT to the noise receiver.

A hybrid in-situ calibration uses tuner data that is already characterized. The same VNA calibrations are still used to determine the 2-port s-parameters from the noise source to the DUT plane, which are then de-embedded to remove the tuner s-parameters. The result will be s-parameter blocks that include everything except the tuner.

After the system TRL calibration, the traditional noise receiver calibration and DUT noise parameter measurement are both done one frequency at a time[3][4]. This is because the noise parameter extraction involves complex math that is sensitive to small errors, and the pattern of source impedance points is important to get well-conditioned data[2]. Measuring one frequency at a time solves this by allowing the impedance pattern to be selected in an optimal manner for each frequency.